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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? single-chip l band to zero if quadrature down converter compliant with 1-45 msps dvb-s2 ? high dynamic range of -92 dbm to -10 dbm without rf attenuator or rssi ? high total composite power handling ? excellent immunity to adjacent channel interference through programmable and autocalibrated channel filters ? integrated power and forget lo oscillators ? 2 degree integrated phase jitter enables excellent performance for 8 psk and 16 qam applications ? less than +/- 3 and +/-0.6 db i/q quadrature balance ? integrated rf loop through for cascaded tuner applications ? power saving mode applications ? advanced modulation dvb-s and dss satellite receivers requiring upgrade for dvb-s2, 8psk/16qam description ZL10038 is a fully integrated tuner for advanced modulation satellite receivers, operating over 950 - 2150 mhz and symbol rates in the range 1 - 45 ms/s. it contains a selectable rf bypass for connecting to a second receiver module. ZL10038 simply requires a crystal reference and operates from a 5 v supply. it is designed as a 'simple to use' stand-alone tuner, requiring no training algorithms or user/demodulator intervention to optimize performance. the ZL10038 can be used with an advanced modulation demodulator to create a highly-integrated front-end solution, operating from 1-45 ms/s. july 2004 ordering information ZL10038/ldg 40-pin qfn (trays) ZL10038/ldg1 40-pin qfn* (trays) ZL10038/ldf 40-pin qfn (tape and reel) ZL10038/ldf1 40-pin qfn* (tape and reel) *pb free -10c to +85c figure 1 - block diagram ZL10038 advanced modulation satellite tuner data sheet
ZL10038 data sheet 2 zarlink semiconductor inc. figure 2 - typical application circuit
ZL10038 data sheet table of contents 3 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.0 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 conventions in this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 quadrature down-converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 agc functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 rf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 baseband . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 rf bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 baseband filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 local oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.1 lo programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 pll frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.7 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 user control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 lock - pin 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.2 sleep - pin 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.3 output ports, p1 & p0 - pins 39 & 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 device address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.1 power-on reset indicator (por bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.2 frequency (& phase) lock (fl bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.3 vco sub-band (sb3:0 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3.4 tune unlock state (tu1:0 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.1 register sub-addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.3 synthesizer division ratio (2 14 :2 0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.4 rf gain (rfg bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.5 baseband pre-filter gain adjust (ba1:0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.6 baseband post-filter gain (bg1:0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.7 rf bypass disable (len bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.8 output port controls (p1 & p0 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.9 power down (pd bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.10 logic reset (clr bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4.11 charge pump control and charge pump current (cc, c1 & c0 bits) . . . . . . . . . . . . . . . . . . . . . 26 3.4.12 reference division ratios (r4:0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.13 baseband filter resistor switching (rsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.14 baseband filter bandwidth (bf6:1 & br4:0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.15 band switch algorithm (vsd bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.16 lo main- & sub-band selection (v2:0 & s3:0 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 3.4.17 lo sample rate (ls2:0 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.18 lo window level (ws, wh2:0 & wl2:0 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 3.4.19 lo window relaxation (wre bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.20 lo test (tl bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.0 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 power-on software initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ZL10038 data sheet table of contents 4 zarlink semiconductor inc. 4.2 changing channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 symbol rate and filter calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.1 determining the filter bandwidth from the symbol rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 calculating the filter bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3 determining the values of bf and br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.4 filter bandwidth programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 programming sequence for filter bandwidth changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.0 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 crystal oscillator notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ZL10038 data sheet list of figures 5 zarlink semiconductor inc. figure 1 - block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - agc control structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5 - typical first stage rf agc response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 - variation in iip2 with agc setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7 - variation in iip3 with agc setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8 - variation in nf with input amplitude (typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9 - rf input and output (bypass) return losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10 - normalized filter transfer characteristic (setting 20 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11 - free running lo phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12 - copper dimensions for optimum heat transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13 - paste mask for reduced paste coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14 - typical oscillator arrangement with optional output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 15 - typical arrangement for external oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ZL10038 data sheet list of tables 6 zarlink semiconductor inc. table 1 - pins by number order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2 - pins by name order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3 - address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4 - read data bit format (msb is transmitted first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5 - tu1/0 functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6 - byte address allocation in write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7 - bit allocations in the write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8 - key to table 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9 - rfg register bit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 10 - ba1/0 register bits function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11 - bg1/0 register bits function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12 - port control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13 - charge pump currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14 - division ratios set with bits r4 - r0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15 - frequency bands and vco gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16 - lo sample rate data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 17 - lo window levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18 - lo recommended window levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 19 - crystal capacitor values for 4 mhz and 10 mhz operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ZL10038 data sheet 7 zarlink semiconductor inc. 1.0 overview 1.1 conventions in this manual hexadecimal values are typically shown as 0xabcdef. binary values (usually of register bits) are shown as 01100 2 . all other numbers should be considered to be decimal values unless specified otherwise. 1.2 pin listings no. name no. name no. name no. name 1 qdc 11 sleep 21 pump 31 rfin 2qdc 12 scl 22 n/c 32 rfin 3qout 13sda 23vvar 33n/c 4qout 14 xtal 24 p0 34 rfagc 5 vccbb 15 xtalcap 25 lock 35 ptest 6 vccbb 16 add 26 vccrf 36 vcclo 7iout 17 digdec 27 rfbypass 37 vcclo 8 iout 18 vccdig 28 rfbypass 38 lotest 9idc 19 vcctune 29 vccrf 39 p1 10 idc 20 drive 30 n/c 40 cnt table 1 - pins by number order name no. name no. name no. name no. add 16 n/c 22 qout 4 vccbb 6 cnt 40 n/c 30 rfagc 34 vccdig 18 digdec 17 n/c 33 rfin 31 vcclo 36 drive 20p0 24rfin 32 vcclo 37 idc 9 p1 39 rfbypass 27 vccrf 26 idc 10 ptest 35 rfbypass 28 vccrf 29 iout 7 pump 21 scl 12 vcctune 19 iout 8 qdc 1 sda 13 vvar 23 lock 25 qdc 2 sleep 11 xtal 14 lotest 38 qout 3 vccbb 5 xtalcap 15 table 2 - pins by name order
ZL10038 data sheet 8 zarlink semiconductor inc. 1.3 pin descriptions pin symbol direction function schematics 1qdc na q channel dc offset correction capacitor. configuration and value as per application diagram (see figure 2). 2qdc na 3qout out q channel baseband differential outputs. ac couple outputs as per applications diagram (see figure 2). 4qout out 5vccbb +5 v voltage supply for baseband 6vccbb +5 v voltage supply for baseband 7iout out i channel baseband differential outputs ac couple outputs as per applications diagram (figure 2). same configuration as pins 3 & 4 8iout out 9idc na i channel dc offset correction capacitor. configuration and value as per application diagram (figure 2). same configuration as pins 1 & 2 10 idc na 11 sleep in hardware power down input. logic ?0? ? normal mode. logic ?1? - analogue sections are powered down. this function is or?ed with the pd control function, see section 3.1.2. 12 scl in i2c serial clock input 13 sda out i2c serial data input/output 10 a internal baseband signal dc correction 10 a internal baseband signal internal baseband signal dc correction dc correction output 1.2 ma vccbb output 1.2 ma vccbb cmos digital input sleep cmos digital input sleep digdec 500k 500k sda/scl input sda only digdec 500k 500k sda/scl input sda only
ZL10038 data sheet 9 zarlink semiconductor inc. 14 xtal in reference oscillator crystal inputs. selected crystal frequency must be programmed in br4 to br0 for correct baseband filter bandwidth operation. xtal pin is used for external reference input via 10nf capacitor. 15 xtalcap out 16 add in variable i2c address selection allowing the use of more than one device per i2c bus system by the voltage on this pin. see table 3 for programming details. 17 digdec out decouple pin for internal digital 3.3 v regulator 18 vccdig +5 v voltage supply for digital logic 19 vcctune varactor tuning +5 v supply 20 drive io loop amplifier output and input pins 21 pump io 22 n/c not connected. ground externally. 23 vvar in lo tuning voltage input pin symbol direction function schematics xtal xtalcap 0.2ma 100 ? digdec 400 ? xtal xtalcap 0.2ma 100 ? digdec 400 ? 20k 60k a dd input digdec 20k 60k a dd input digdec digdec vccdig digdec vccdig drive 3k pump cpdec vcctune drive 3k pump cpdec vcctune vvar 1 k vbias vvar 1 k vbias
ZL10038 data sheet 10 zarlink semiconductor inc. 24 p0 out switching port p0. ?0? = disabled (high impedance). ?1? = enabled. 25 lock out output which indicates that phase comparator phase and frequency lock has been obtained and that the varactor voltage is within ?tune unlock? window. this powers up in logic ?0? state. 26 vccrf +5 v voltage supply for rf 27 rfbypass out rf bypass differential outputs. ac couple outputs. matching circuitry as per applications diagram (figure 2). in applications where rf bypass is not required, pins should not be connected. 28 rfbypass out 29 vccrf +5 v voltage supply for rf 30 n/c not connected. ground externally. 31 rfin in rf differential inputs. ac couple input. matching circuitry as per applications diagram. 32 rfin in 33 n/c not connected. ground externally. 34 rfagc in rf analogue gain control input pin symbol direction function schematics p0/p1 p0/p1 lock cmos digital output lock cmos digital output vccrf rfagc 5k 20k vref vccrf rfagc 5k 20k vref
ZL10038 data sheet 11 zarlink semiconductor inc. 35 ptest in connected to internal circuit for monitoring die temperature 36 vcclo +5 v voltage supply for lo 37 vcclo +5 v voltage supply for lo 38 lotest io bi-directional test port for accessing internal lo ac couple input. 39 p1 out switching port p1 ?0? = disabled (high impedance) ?1? = enabled same configuration as pin 24, p0 40 cnt bonded to paddle. production continuity test for paddle soldering note : exposed paddle on rear of package must be connected to gnd. pin symbol direction function schematics ptest ptest lotest vcclo bias lotest vcclo bias
ZL10038 data sheet 12 zarlink semiconductor inc. 2.0 functional description figure 3 - detailed block diagram 2.1 quadrature down-converter in normal applications the tuner rf input frequency of 950 - 2150 mhz is fed directly to the ZL10038 rf input preamplifier stage, through an appropriate impedance match. the input preamplifier is optimized for nf, s11 and signal handling. the signal handling of the front end is designed such that no tracking filter is required to offer immunity to input composite overload.
ZL10038 data sheet 13 zarlink semiconductor inc. 2.2 agc functions the ZL10038 contains an analogue rf agc combined with digitally controlled gain for rf, baseband pre-filter and post-filter, as described in figure 4. the baseband agc is controlled by the i2c bus and is divided into pre- and post-baseband filter stages, each of which have 12.6 db of gain adjust in 4.2 db steps. the rf agc is provided as the dynamic system gain adjust under control of the baseband analogue agc output function whereas the digitally controlled gains are provided to maximize performance under different signal conditions. the total agc gain range will guarantee an operating dynamic range of -92 to -10 dbm. the digitally controlled rf gain adjust and the baseband pre-filter stage can be adjusted in sympathy to maintain a fixed overall conversion gain. the lower rf gain setting would be used in situations where for example there is a high degree of cable tilt or high desired to undesired ratio, whereas the higher rf gain setting would be used in situations where for example it is desirable to minimize nf. the baseband post-filter gain stage can be used to provide additional gain to maintain desired output amplitude with lower symbol rate applications. figure 4 - agc control structure 2.2.1 rf the rf input amplifier feeds an agc stage, which provides for rf gain control. figure 5 - typical first stage rf agc response normalized gain range in db: 0 - 72 0 or +4 0 to 12.6 in 4.2 db steps 0 to 12.6 in 4.2 db steps gain function: rf agc stepped stepped stepped control function: analogue voltage i2c bus i2c bus i2c bus -80 -70 -60 -50 -40 -30 -20 -10 0 10 00.511.522.533.544.55 agc control voltage v conversion gain relative to max gain (db)
ZL10038 data sheet 14 zarlink semiconductor inc. the rf agc is divided into two stages. the first stage is a continually variable gain control stage, which is controlled by the agc sender and provides the main system agc set under control of the analogue agc signal generated by the demodulator section. the second stage is a bus programmable. two-position gain set previous to the quadrature mixer and provides for 4 db of gain adjust under software control. the analogue rf agc is optimized for s/n and s/i performance across the full dynamic range. the rf agc characteristic, variation of iip2, iip3 and nf are contained in figure 6, figure 7 & figure 8 respectively. the rf preamplifier is also coupled to the selectable rf bypass, which is described in 2.3, ?rf bypass?. the specified electrical parameters of the rf input are unaffected by the rf bypass state. figure 6 - variation in iip2 with agc setting (rf gain adjust = +0 db, prefilter = +4.2 db and postfilter = 4.2 db, baseband filter bandwidth = 22 mhz) figure 7 - variation in iip3 with agc setting (rf gain adjust = +0 db, prefilter = +4.2 db and postfilter = 4.2 db, baseband filter bandwidth = 22 mhz) -10 -5 0 5 10 15 20 25 30 35 10 20 30 40 50 60 70 80 gain setting db iip2 dbm -50 -40 -30 -20 -10 0 10 20 20 30 40 50 60 70 80 gain setting db iip3 dbm
ZL10038 data sheet 15 zarlink semiconductor inc. figure 8 - variation in nf with input amplitude (typical) the output of the rf agc stage is coupled to the quadrature mixer where the rf input is mixed with quadrature lo (local oscillator) signals generated by the on-board lo. operation and control of the lo is described further in section 2.5 on page 17. 2.2.2 baseband the mixer outputs are coupled to the baseband quadrature channel amplifier and filter stage, which is of 7th order topology. operation and control of the baseband filter is contained in section 2.4 on page 16. the baseband paths are dc coupled, and include a dc correction loop. the high pass characteristic for the dc correction loop is defined by the off chip capacitor connected to pins ?idc/idc ? and ?qdc/qdc ?. the output of each channel stage is designed for low impedance drive capability and low intermodulation and can be loaded either differentially or single-ended; in the case of single-ended load the unused output should be unloaded. the maximum output load is defined in the electrical characteristics table. 0 10 20 30 40 50 60 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 input amplitude (dbm) nf (db) rf programmable gain = 4db, prefilter gain = 4.2db, post filter gain = 0db baseband output level = 0.5vp-p
ZL10038 data sheet 16 zarlink semiconductor inc. 2.3 rf bypass the ZL10038 provides an independent bypass function, which can be used for driving a second receiver module. the electrical characteristics of the rf input are unchanged by the state of the rf bypass. the bypass provides a differential buffered output from the input signal with a nominal 3.5 db gain. the unused output should be terminated as in figure 2 on page 2. the bypass function is enabled by a single register bit and is not disabled by either the pd bit or the sleep pin. when disabled the bypass function is in a ?power-down? state. on power up the bypass function is enabled. figure 9 - rf input and output (bypass) return losses 2.4 baseband filter the filter bandwidth is controlled by a frequency locked loop (fll) the timing of which is derived from the reference crystal source by a reference divider. five control bits set the system reference division ratio and the baseband filter bandwidth can be programmed with a further six control bits for a nominal range of 4 - 40 mhz 1 . 1. specification compliant over the range 8 - 35 mhz. -30 -25 -20 -15 -10 -5 0 900 100 0 110 0 12 0 0 13 0 0 14 0 0 15 0 0 16 0 0 17 0 0 18 0 0 19 0 0 200 0 210 0 220 0 frequency (m h z) return loss (db) s11 rfbypass on s22 rfbypass on
ZL10038 data sheet 17 zarlink semiconductor inc. figure 10 - normalized filter transfer characteristic (setting 20 mhz) the -3 db bandwidth of the filter (hz) is given by the following expression: where: f -3db = baseband filter ?3 db bandwidth (hz) which should be within the range . f xtal = crystal oscillator reference frequency (hz). k = 1.257 (constant). bf = decimal value of the register bits bf6:bf1, range 0 - 62. br = decimal value of the bits br4:br0 (baseband filter reference divider ratio), range 4 - 27. = 575 khz to 2.5 mhz. methods for determining the values of br and bf are given in the section on software, please see sect. 4.3 on page 30. 2.5 local oscillator the lo on the ZL10038 is fully integrated and consists of three oscillator stages, each with 16 sub-bands. these are arranged such that the regions of operation for optimum phase noise are continuous over the required tuning range of 950 to 2150 mhz and over the specified operating ambient conditions and process spread. the local oscillators operate at a harmonic of the required frequency and are divided down to the required lo conversion frequency. for each of the three oscillators, the lo prescaler ratio (n lp ) is set to 4 or 2. the required divider ratio is automatically selected by the lo control logic, hence programming of the required conversion frequency across the oscillator bands is automatic and requires no intervention by the user. f -3db f xtal br ---------- bf 1 + () 1 k --- - = 8mhz f 3db ? 35mhz ? f xtal br ---------
ZL10038 data sheet 18 zarlink semiconductor inc. figure 11 - free running lo phase noise performance the oscillators are designed to deliver good free running phase noise at 10 khz offset, therefore the required integrated phase jitter from the lo can be achieved without the requirement for running with a high comparison frequency and hence large tuning increment and wide loop bandwidth. the lo section contains an internal tuning controller, which will automatically tune to the appropriate vco and sub band for optimum phase noise performance. the internal lo controller function is transparent to the user and no user intervention is required. the tuning controller will automatically switch bands when required, however this function can be disabled with the ? vsd ? bit (see ?3.4.15?). this enables the user to select the appropriate vco and sub band if required to achieve optimum phase noise performance. for qpsk, automatic mode will be adequate and should be used. in general for 8 psk modulation, the automatic mode will also be adequate depending on the demodulator requirements. 16 qam may require manual mode to optimize phase noise performance at frequencies above 1800 mhz. 2.5.1 lo programming the controller tunes across the oscillator bands, until lock is achieved. the algorithm for tuning utilises the lo tuning voltage, vvar, which is compared at a programmable sample rate against a ?tune lock? voltage window and a ?tune unlock? voltage window. the sampling rate default on power up is fcomp/8 however this can be programmed into further rates through bits ls2-ls0 in byte-10, see ?3.4.17? on page 29. the ?tune lock? and ?tune unlock? windows are set at default values, however, these can be adjusted by bits ws , wh2:0 and wl2:0 in byte 11, see ?3.4.18? on page 29. in the event that the controller is unable to find lock the ?tune lock? window will be automatically widened. this facility can be disabled by setting bit wre in byte 11 to logic ?0?. see 3.4.19 on page 30. the device has a lock indicator flag, fl , which is derived from a time averaged phase comparison between the lo divider and reference divider inputs to the phase comparator. the fl flag is read in the status byte. see 3.3.2 on page 21. there is a further hardware lock flag (lock output, pin 25; see ?3.1.1? on page 20) which generates a logic ?0? if the tuning controller detects the varactor line voltage lies within the ?tune unlock? window and if fl is set to logic ?1?. in other states this output is high impedance. -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 10 100 1000 10000 100000 frequency offset (log (offset in khz)) phase noise (dbc/hz)
ZL10038 data sheet 19 zarlink semiconductor inc. the tune lock window is centralised within the tuner unlock window. the tuning controller selects the vco and sub band so that the varactor voltage is within this window. if this is not possible the lock windows are relaxed (assuming the wre bit is set to '1'). the tuning algorithm maintains a level of hysteresis to prevent short term drift causing switching to an adjacent band. the lo control logic has provision for master reset to restore initial set up conditions. this is controlled by bit clr within data byte 13, see ?3.4.10? on page 25. 2.6 pll frequency synthesizer the pll frequency synthesizer section contains all the elements necessary, with the exception of a frequency reference and loop filter to control a varicap tuned lo, so forming a complete pll frequency synthesized source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the loop can also be operated up to comparison frequencies of 2 mhz enabling application of a wide loop bandwidth for maximizing the close in phase noise performance. the lo input signal is multiplexed from the selected oscillator band to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces direct with the 15-bit fully programmable divider, which is of mn+a architecture. a 16/17 dual modulus prescaler is used. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider, which is programmable into one of 29 ratios as detailed in table 14 on page 26. the typical application for the crystal oscillator is contained in figure 2. the output of the phase detector feeds a charge pump and loop amplifier section. this combined with an external loop filter integrates the current pulses into the varactor line voltage with an output range of vee to vcctune. the varactor line voltage is externally coupled to the oscillator section through the input vvar, enabling application of a third order loop. control of the charge pump current can be made in two ways as described in table 13 on page 26. either the set charge pump current can be used at all times, or the charge pump current can be scaled automatically according to the lo sub-band. the second case allows for reduced loop bandwidth variation as the vco gain varies with sub-band. 2.7 control logic the ZL10038 is controlled by an i2c data bus and can function as a slave receiver or slave transmitter compatible with 3v3 or 5 v levels. data and clock are input on the sda and scl lines respectively as defined by i2c bus standard. the device can either accept data (slave receiver, write mode), or send data (slave transmitter, read mode). the lsb of the address byte (r/w ) sets the device into write mode if it is logic ?0?, and read mode if it is logic ?1?. table 4 and table 7 illustrate the format of the read and write data respectively. the device can be programmed to respond to one of four addresses, which enables the use of more than one device in an i2c bus system if required for use in pvr 1 systems, for example. table 3 shows how the address is selected by applying a voltage to the address, ? add ?, input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal stop condition, which inhibits further reading. 1. pvr - personal video recorder where dual tuners allow the viewer to watch one channel and record another simultaneously, usu ally to a hard-disk recording system.
ZL10038 data sheet 20 zarlink semiconductor inc. all the ZL10038 functions are controlled by register bits written through the i2c bus interface. the sleep pin can be used to power-down the device, but it can also be put into the power-down mode with the pd register bit, the two functions being logically or?ed. feedback on the status of the ZL10038 is provided through eight bits in the status byte register and the phase lock state is also available on the lock output pin (as well as the fl register bit). 3.0 user control 3.1 i/o pins the i2c interface controls all the major functions. apart from the various analogue functions, the only pins that either control the ZL10038, or are controlled by the internal logic, are the lock , sleep , p1, p0 and add pins. details follow: 3.1.1 lock - pin 25 this is an output which indicates phase frequency lock on the correct vco sub band for optimum phase noise. the cmos output can directly drive a low power led if required. 3.1.2 sleep - pin 11 the sleep pin shuts down the analogue sections of the device to give a considerable power saving, typically reducing the power to about one third of its normal level. the rf-bypass function is entirely separate and is unaffected by the state of this pin. the sleep pin?s function is or?ed with the pd register bit (see ?3.4.9? on page 25), so that if either is a logic one, the zl10036 will be powered down, or alternatively, both must be at logic zero for normal operation. 3.1.3 output ports, p1 & p0 - pins 39 & 24 two open-collector ports are provided for general purpose use, under control of register bits p1 and p0 . the default at power-up is for the p1 & p0 register bits to be low, hence the outputs will be off, i.e., in their high-impedance states. if connected to a pull-up resistor this will therefore result in a logic high. setting a register bit high will turn the corresponding output on and therefore pull the logic level to near 0 v giving a logic low. 3.2 device address selection two internal logic levels, ma1 and ma0 , can be set to one of four possible logic states by the voltage applied to the add pin (#16). these four states in turn define four different read and write addresses on the i2c bus, so that as many as four separate devices can be individually addressed on one bus. this is of particular use in a multi-tuner environment as required by pvr applications. add pin voltage ma1 ma0 write address read address hex. dec. hex. dec. vee (0 v or gnd) 0 0 0xc0 192 0xc1 193 open circuit 0 1 0xc2 194 0xc3 195 0.5 * digdec (20%) 1 1. can be programmed with a single 30 k ? resistor to digdec 1 0 0xc4 196 0xc5 197 digdec 1 1 0xc6 198 0xc7 199 table 3 - address selection
ZL10038 data sheet 21 zarlink semiconductor inc. 3.3 read register the ZL10038 status can be read by addressing the device in its slave transmitter mode by setting the lsb of the address byte (the r/w bit) to a one. after the master transmits the correct address byte, the ZL10038 will acknowledge its address, and transmit data in response to further clocks on the scl input. if the master responds with an acknowledge and further clocks, the status byte will be retransmitted until such time as the master fails to send an acknowledge, when the ZL10038 will release the data bus, allowing the master to generate a stop condition. the individual bits in the status register have the following meanings: 3.3.1 power-on reset indicator (por bit) this bit is set to a logic ?1? if the vccdig supply to the pll section has dropped below typically 3.6 v, e.g., when the device is initially turned on. the bit is reset to ?0? when the read sequence is terminated by a stop command. when the por bit is high, this indicates that the programmed information may have been corrupted and the device reset to power up condition. 3.3.2 frequency (& phase) lock (fl bit) bit 6 (fl) indicates whether the synthesizer is phase locked, a logic ?1? is present if the device is locked and a logic ?0? if the device is unlocked. 3.3.3 vco sub-band (sb3:0 bit) these bits indicate the vco sub-band value chosen by the lo tuning algorithm when tuning the oscillators automatically. if manual tuning is used then sb3-sb0 will match bits s3-s0 written to register byte 9 (see ?3.4.16? for sub-band details). 3.3.4 tune unlock state (tu1:0 bit) these bits define the ?tune unlock? window state as below: see ?lo window level (ws, wh2:0 & wl2:0 bits)? on page 29 for further information on the threshold voltages. bit no. 7 (msb) 6543210 (lsb) address 1 1000ma1ma01 status por fl sb3 sb2 sb1 sb0 tu1 tu0 table 4 - read data bit format (msb is transmitted first) tu1 tu0 ?tune unlock? window state 0 0 vvar between lower and upper voltage thresholds 0 1 vvar above upper voltage threshold 1 0 vvar below lower voltage threshold 1 1 undefined - do not use table 5 - tu1/0 functions
ZL10038 data sheet 22 zarlink semiconductor inc. 3.4 write registers the ZL10038 has twelve registers which can be programmed by addressing the device in its slave receiver mode, setting the lsb of the address byte (the r/w bit) to a zero. after the master transmits the correct address byte, the ZL10038 will acknowledge its address, and accept data in response to further clocks on the scl line. at the end of each byte, the ZL10038 will generate the acknowledge bit. the master can at this point, generate a stop condition, or further clocks on the scl line if further registers are to be programmed. if data is written after the twelfth register (byte-13), it will be ignored. 3.4.1 register sub-addressing if some register bits require changing, but not all, it is not necessary to write to all the registers. the registers can be addressed in pairs starting with the even numbered bytes, i.e., 2 & 3, 4 & 5, etc. table 6 below shows the protocol required to address any of the even numbered register bytes. it therefore follows that to write to register byte-7 for instance, byte-6 must also be written first. register pairs may be written in any order, as required by the software, e.g., 10/11 may be followed by 4/5. data bits byte selected 7 (msb) 654 0xxx 2 10xx 4 1 100 6 1 101 8 1 110 10 1 111 12 ?x? = don?t care (content defines a register bit). table 6 - byte address allocation in write mode
ZL10038 data sheet 23 zarlink semiconductor inc. 3.4.2 register mapping byte bit no. function 7 (msb) 6543210 (lsb) reset state (hex.) 1 1. this is the power-on default register value - recommended operating values may be different, see ?4.1? on page 30. further information 1 device address11000ma1ma00 table 3 on page 20 2 programmable divider 02 14 2 13 2 12 2 11 2 10 2 9 2 8 0x00 see 3.4.3 on page 24 3 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0x00 4 control data 1 0 rfg ba1 ba0 bg1 bg0 len 0x80 ?3.4.4? to ?3.4.7? on p. 25 5 p0 c1 c0 r4 r3 r2 r1 r0 0x00 pp. 25 & 26 6 1100rsd0000xc0 see ?3.4.13? on page 27 7 p1 bf6 bf5 bf4 bf3 bf2 bf1 0 0x20 pp. 25 & 27 8 11010cc110xdb page 26 9 vsd v2 v1 v0 s3 s2 s1 s0 0x30 page 28 10 11100ls2ls1ls00xe1 page 29 11 ws wh2 wh1 wh0 wl2 wl1 wl0 wre 0x75/f5 page 29 12 111100000xf0 test function only 13 pd br4 br3 br2 br1 br0 clr tl 0x28 pp. 25, 27 & 30 table 7 - bit allocations in the write registers symbol definition symbol definition 2 14 -2 0 programmable division ratio control bits r4-r0 reference division ratio select ba1-0 baseband prefilter gain adjust rfg rf programmable gain adjust bf6-1 baseband bandwidth adjust rsd resistor switch disable bg1-0 baseband postfilter gain adjust s3-0 lo sub-band select br4-0 baseband filter fll reference frequency select tl buffered lo output select c1,c0 charge pump current select pd power down cc charge pump control v2-0 lo main band select clr control logic reset vsd lo tuning algorithm disable len rf bypass enable wh2-0 lo window high level adjust ls2-0 tuning control sampling rate adjust wl2-0 lo window low level adjust ma1,ma0 variable address bits wre tuning window relaxation enable p0, p1 external switching ports ws tuning window select table 8 - key to table 7
ZL10038 data sheet 24 zarlink semiconductor inc. 3.4.3 synthesizer division ratio (2 14 :2 0 bits) the pll synthesizer interfaces with the lo multiplex output and runs at the desired frequency for down-conversion. the step size at the desired conversion frequency, is equal to the loop comparison frequency. the programmable division ratio, 2 14 to 2 0 , required for a desired conversion frequency, can be calculated from the following formula: desired conversion frequency = where: ? f step = fcomp 3.4.4 rf gain (rfg bit) the rf gain is programmed by setting the rfg bit, bit-5 of register byte-4 as required. see also figure 4, ?agc control structure? on page 13. 3.4.5 baseband pre-filter gain adjust (ba1:0 bits) the baseband pre-filter gain is programmed by setting ba1:0 , bits-4 & 3 of register byte-4 as required. see also figure 4, ?agc control structure? on page 13. 3.4.6 baseband post-filter gain (bg1:0 bits) the baseband post-filter gain is programmed by setting bg1:0 , bits-2 & 1 of register byte-4 as required. see also figure 4, ?agc control structure? on page 13. rfg gain adjust (db) 0 0 (reset state) 1+4 table 9 - rfg register bit function ba1 ba0 pre-filter gain adjust (db) 0 0 0.0 (reset state) 01 +4.2 10 +8.4 11 +12.6 table 10 - ba1/0 register bits function bg1 bg0 post-filter gain adjust (db) 0 0 0.0 (reset state) 01 +4.2 10 +8.4 1 1 +12.6 table 11 - bg1/0 register bits function ? f step 2 14 2 13 2 12 2 2 2 1 + 2 0 ++ + ()
ZL10038 data sheet 25 zarlink semiconductor inc. 3.4.7 rf bypass disable (len bit) the rf bypass function is disabled by setting len , bit-0 of register byte-4 to a logic ?1?. by default, this bit is at a logic ?0? at power-up, and therefore the function is enabled. if the function is not required, a power saving of approximately 15% can be made by setting this bit. see also section 2.3 on page 16. 3.4.8 output port controls (p1 & p0 bits) register bits p1 and p0 , bit-7 in register bytes-7 & 5 respectively, control the output port pins, p1 & p0, pin numbers 39 & 24 respectively. 3.4.9 power down (pd bit) bit-7 of byte-13 controls the pd register bit which is an alternative to the sleep pin (see ?sleep - pin 11? on page 20). setting the pd bit to a logic ?1? shuts down the analogue sections of the ZL10038 effecting a saving of about 2/3rds of the power required for normal operation. a logic ?0? restores normal operation. with either hardware or software power-down, all register settings are unaffected. 3.4.10 logic reset (clr bit) bit-1 of byte-13 controls the clr register bit. when set to a logic ?1?, this self-clearing bit resets the zl10036 control logic. writing a logic ?0? has no effect. the following register numbers are reset to their power-on state: 7, 9, 10, 11, 12 & 13. all other register?s contents are unaffected. bit p1 or p0 port state logic state (if connected to a pull-up) 0 high impedance 1 (reset state) 1 low impedance to vee (gnd) 0 table 12 - port control bits
ZL10038 data sheet 26 zarlink semiconductor inc. 3.4.11 charge pump control and charge pump current (cc, c1 & c0 bits) register bit cc is programmed by setting bit-2 of register byte-8 and bits c1 and c0 by setting bits-6 & 5 of register byte-5. these bits determine the charge pump current that is used on the output of the frequency synthesizer phase detector. 3.4.12 reference division ratios (r4:0 bits) register bits r4:0 control the reference divider ratios as shown in table 14. they are programmed through bit-4 to bit-0 respectively, in byte-5. cc c1 c0 typical current in a vco sub-bands 0 - 7 vco sub-bands 8 - 15 0 0 0 365 210 (reset state) current limits 001 625 365 min. typ. max. 0 1 0 1065 625 160 210 290 0 1 1 invalid setting 280 365 510 1 0 0 210 470 625 860 1 0 1 365 820 1065 1470 110 625 1 1 1 1065 table 13 - charge pump currents r4 00 1 1 r3 01 0 1 r2 r1 r0 division ratios 000 2 illegal states 001 4567 010 8101214 011 16 20 24 28 100 32 40 48 56 101 64 80 96 112 110 128 160 192 224 111 256 320 384 448 table 14 - division ratios set with bits r4 - r0
ZL10038 data sheet 27 zarlink semiconductor inc. 3.4.13 baseband filter resistor switching (rsd) the baseband filters use a resistor switching technique that improves bandwidth and phase matching between the i and q channels. the bandwidth range is effectively separated into 3 sub-ranges with different resistor values being used in each sub-range. it is possible for the filter bandwidth accuracy to be degraded if the bandwidth setting happens to coincide with one of the two transition points between these regions. this can be overcome by disabling the resistor switching using the rsd bit. for optimum filter performance the rsd bit should first be enabled so that the correct resistor value is automatically set for the selected bandwidth. the rsd bit (bit-3 of byte-6) controls the resistor switching. with the default setting of logic '0' it is enabled and the correct resistor value automatically chosen. with the rsd bit set to a logic '1' then the switching is disabled and this freezes the resistors at their chosen value. the procedure when selecting a new bandwidth setting is to enable then disable the switching; set rsd to logic '0' then to logic '1'. 3.4.14 baseband filter bandwidth (bf6:1 & br4:0 bits) bits 6 to 1 of byte-7 configure bits bf6 to bf1 respectively. these bits set a decimal number in the range 0 to 62 (63 is not allowed) to determine the baseband filter bandwidth in conjunction with other values. bits 6 to 2 of byte-13 configure bits br4 to br0 respectively. these bits set the reference divider ratio for the baseband filter. a number in the range 4 to 27 inclusive (values outside this range are not allowed) can be set, with the proviso that the value of f xtal /br4:0 must also be in the range 575 khz to 2,500 khz. for further details, please also see ?baseband filter? (sect. 2.4) on page 16 and ?symbol rate and filter calculations? (sect. 4.3) on page 30. 3.4.15 band switch algorithm (vsd bit) the controller, which tunes to the appropriate lo and sub band for optimum phase noise performance, can be disabled with the vsd bit, if required, allowing manual control. the vsd bit is programmed using byte-9, bit-7. the default is for the controller to be enabled, vsd = ?0?, and to disable the controller a logic ?1? is written to this bit.
ZL10038 data sheet 28 zarlink semiconductor inc. 3.4.16 lo main- & sub-band selection (v2:0 & s3:0 bits) if manual control of the lo is selected with the vsd bit, bits v2:0 (main-band) and s3:0 (sub-band) can be used to set the lo frequency band. values of v2:0 from 1 to 6 are valid, values 0 and 7 being used for test purposes only. the prescaler ratio, n lp , is set to ?4? for values of v2:0 from 1 to 3 and to ?2? for v2:0 from 4 to 6. table 15 shows typical minimum and maximum frequencies for each vco and sub band for a varactor voltage (vvar) range of 3 to 4.5 volts. this is the normal varactor operating voltage, however the vco will operate at lower voltages if required. the vco gain is also shown at 3.5 volts varactor voltage. table 15 - frequency bands and vco gain s3 s2 s1 s0 min max kvco min max kvco min max kvco 0000 690 699 6.9 881 892 8.9 1068 1081 10.0 0001 697 708 7.3 892 905 9.3 1080 1094 10.6 0010 706 716 7.8 904 917 9.7 1093 1108 11.2 0011 714 726 8.3 917 930 10.1 1107 1122 11.9 0100 725 737 8.9 931 946 10.9 1122 1139 13.1 0101 735 748 9.6 945 960 11.6 1138 1156 14.1 0110 746 761 10.3 959 976 12.4 1154 1174 15.1 0111 759 774 11.2 975 992 13.4 1173 1194 16.4 1000 769 786 12.2 986 1005 14.5 1182 1205 17.5 1001 783 801 13.2 1003 1024 15.8 1203 1227 19.1 1010 798 817 14.4 1021 1044 17.2 1224 1251 20.8 1011 814 836 15.7 1041 1066 19.0 1248 1278 22.9 1100 834 857 17.4 1063 1092 21.7 1275 1309 26.4 1101 853 879 19.0 1087 1119 24.4 1303 1341 29.6 1110 874 902 20.8 1112 1148 27.5 1334 1376 33.3 1111 896 927 23.1 1141 1182 31.6 1368 1415 37.7 s3 s2 s1 s0 min max kvco min max kvco min max kvco 0000 1380 1399 13.8 1761 1785 17.8 2136 2162 19.9 0001 1395 1415 14.6 1785 1809 18.6 2161 2188 21.2 0010 1411 1433 15.5 1809 1835 19.3 2186 2215 22.4 0011 1429 1451 16.5 1834 1861 20.3 2214 2245 23.9 0100 1450 1474 17.9 1862 1891 21.9 2244 2278 26.1 0101 1470 1496 19.2 1889 1920 23.2 2276 2312 28.1 0110 1493 1521 20.7 1918 1951 24.8 2309 2348 30.2 0111 1517 1548 22.4 1949 1985 26.8 2345 2388 32.7 1000 1538 1571 24.3 1972 2011 29.1 2365 2410 35.1 1001 1565 1601 26.4 2006 2048 31.6 2405 2455 38.3 1010 1595 1635 28.7 2042 2088 34.5 2449 2502 41.7 1011 1628 1671 31.4 2082 2132 38.1 2497 2555 45.9 1100 1667 1714 34.7 2126 2183 43.4 2550 2617 52.9 1101 1706 1758 38.0 2174 2238 48.9 2607 2682 59.1 1110 1747 1804 41.6 2225 2296 55.1 2668 2752 66.5 1111 1793 1855 46.1 2282 2364 63.2 2736 2830 75.4 v0 divider v2 v1 1 0 1 divider v2 v1 v0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 vco2 2 vco3 2 vco3 4 vco1 2 1 vco1 4 vco2 4
ZL10038 data sheet 29 zarlink semiconductor inc. 3.4.17 lo sample rate (ls2:0 bits) bits ls2:0 (bit-2 to bit-0 respectively in byte-10) set the lo sample rate according to the following table: 3.4.18 lo window level (ws, wh2:0 & wl2:0 bits) byte-11 allows the user to change the lock and unlock window voltages that the tuning controller uses in comparison with the vvar input. setting the ws bit to ?0? allows the lock levels to be altered, or if set to ?1?, the unlock levels are written. the wh2:0 bits set the upper levels and the wl2:0 bits set the lower levels in each case. please see ?power-on software initialization? (sect. 4.1) on page 30 for recommended values. ls2 ls1 ls0 sample rate 000 f comp /4 001 f comp /8 (reset state) 010 f comp /16 011 f comp /32 100 f comp /64 101 f comp /128 110 f comp /512 111f comp /2048 table 16 - lo sample rate data lock unlock ws 0 1 wh2 wh1 wh0 lower upper lower upper wl2 wl1 wl0 0 0 0 1.16 1.54 1.08 1.61 0 0 1 1.64 2.01 1.56 2.08 010 2.11 2.47 2.03 2.55 0 1 1 2.57 2.94 2.50 3.01 1 0 0 3.03 3.43 2.95 3.51 1 0 1 3.49 3.89 3.42 3.97 1 1 0 3.95 4.36 3.88 4.43 1 1 1 4.41 4.82 4.34 4.89 key: reset values table 17 - lo window levels
ZL10038 data sheet 30 zarlink semiconductor inc. 3.4.19 lo window relaxation (wre bit) in the event of the controller failing to lock due to the lock window being too narrow, the window is automatically widened when wre (byte-11 bit-0) is ?1? in order to achieve lock. the wre bit, when set to logic ?0?, disables this facility. 3.4.20 lo test (tl bit) for test purposes, the lo clock divided by the prescaler ratio can be output on the lotest pin by setting bit tl (byte-13 bit-0) to a logic ?1?. by default this output is off, i.e., the tl bit is at logic ?0?. 4.0 software in normal operation, only initialization, channel (frequency) changes and symbol rates require programming intervention. note that the pll comparison frequency is set by the crystal frequency divided by the pll reference divide ratio. in the following examples of register settings, binary values are frequently used, indicated as e.g., 0110 2 . 4.1 power-on software initialization a. bytes 2 + 3: 2 14 -2 0 = desired channel frequency/pll comparison frequency (vco = 3, sub-band = 0, divider = 4 is default, means that the local oscillator frequency will be about 1.1 ghz). b. byte 4: ba1:0 = 01 2 for initial baseband filter input level. c. byte 4: bg1:0 = 01 2 for target baseband filter output level. d. byte 4: len = 1 if the rf loop through is to be disabled. e. byte 5: r4:0 = pll reference divider for desired comparison frequency. f. byte 8: ps = 0 to give a pre-scaler ratio of 16/17. bits ?0? & ?1? should be set to 00 2 . g. byte 11: wl2:0 and wh2:0 may require different values from the defaults. recommended settings are: h. byte 13: br4:0 = crystal frequency in use (see also 4.3.3.1 on page 31). 4.2 changing channel bytes 2 + 3: 2 14 -2 0 = channel frequency/pll comparison frequency. 4.3 symbol rate and filter calculations 4.3.1 determining the filter bandwidth from the symbol rate f bw = ( * symbol rate)/(2.0 * 0.8) + f offs where: = 1.35 for dvb or 1.20 for dss, and is the roll-off of the raised-root cosine filter in the transmitter, ws wh2 wh1 wh0 wl2 wl1 wl0 wre lower v upper v lock011010113.49 3.89 unlock111110012.95 4.89 table 18 - lo recommended window levels
ZL10038 data sheet 31 zarlink semiconductor inc. f offs is the total offset of the received signal due to all causes (lnb drift, synthesizer step size, etc) and is read back from the demodulator, and f bw is the -3 db roll-off of the filter for: 8 mhz f bw 35 mhz. for low symbol rates, the energy content within the bandwidth of the filters reduces significantly so incrementing the baseband post-filter gain helps recover the signal level for the demodulator. n.b. during channel acquisition or re-acquisition, the filter must be set to its maximum value. 4.3.2 calculating the filter bandwidth the -3 db bandwidth of the filter (hz) is given by the following expression: equation 1 - where: f bw = baseband filter ?3 db bandwidth (hz) which should be within the range . f xtal = crystal oscillator reference frequency (hz). k = 1.257 (constant). bf = decimal value of the register bits bf6:bf1, range 0 - 62. br = decimal value of the bits br4:br0 (baseband filter reference divider ratio), range 4 - 27. where: 575 khz 2.5 mhz. the digital nature of the control loop means that the filter bandwidth setting is quantized: the difference between the desired filter bandwidth and the actual filter bandwidth possible due to discrete settings causes a bandwidth error. in order to minimize this bandwidth error, the maximum filter bandwidth setting resolution is needed. from the limits given above, the best resolution possible is 575 khz/1.257 = 457.4 khz. however if this resolution is used, the maximum bandwidth with bf = 62 is only 28.82 mhz, below the maximum of 35 mhz. therefore for filter bandwidths greater than 28.82 mhz the resolution must be decreased. for filter bandwidths around 35 mhz the resolution is typically reduced to 698 khz/1.257 = 555.3 khz. 4.3.3 determining the values of bf and br 4.3.3.1 calculating the value of br the above description can be described mathematically as: for f bw 28.82 mhz, equation 2 - . for f bw > 28.82 mhz, equation 3 - . these equations can give non-integer results so rounding must be performed. the values for br should be rounded down to the nearest integer this ensures that will not be below 575 khz and that the maximum programmable bandwidth will not be below the desired bandwidth due to rounding. f bw f xtal br ---------- bf 1 + () 1 k --- - = 8mhz f bw 35mhz ? f xtal br --------- br f xtal 575khz ------------------- - = br f xtal f bw -------- 62 1 + () 1 k --- - = f xtal br -------- -
ZL10038 data sheet 32 zarlink semiconductor inc. 4.3.3.2 calculating the value of bf equation 4 - for non-integer values of bf, the result should be simply rounded to the nearest integer to give the value for bf6:1. 4.3.4 filter bandwidth programming examples example 1, conditions: f xtal = 10.111 mhz, f bw = 9 mhz because f bw is below 28.2 mhz, the value of br can be evaluated with equation 2: this result should be rounded down to 17 to ensure that the result is not below the 575 khz limit. using this value for br, equation 4 can be evaluated: the result can be rounded to the nearest value, i.e. bf = 18. example 2, conditions: f xtal = 10.111 mhz, f bw = 34.6 mhz in this case, f bw is above 28.2 mhz so using equation 3 to solve for br: using equation 4, this time with the rounded-down value of 14 for br: rounding to the nearest integer thus gives a value of 59 for bf. 4.4 programming sequence for filter bandwidth changes a. byte 6: set rsd = 0 to re-enable baseband filter resistor switching. b. byte 7: set bf6:1 to the value derived in 4.3.3.2, ?calculating the value of bf? on page 32. c. byte 6: set rsd = 1 to disable baseband filter resistor switching. this must happen no sooner than a certain time after (b.). this minimum time equals br/(32 * f xtal ) seconds, where br is the decimal value of byte br and f xtal is the reference crystal frequency. bf f bw f xtal -------- br k ?? ?? 1 ? = = br f xtal 575khz ------------------- - 10.111mhz 575khz ------------------------------ 1 7 . 5 8 3 == = bf f bw f xtal -------- br k ?? ?? 1 ? 9mhz 10.11mhz -------------------------- - 17 1.257 ?? ?? 1 ? 18.02285 == = br f xtal f bw -------- 63 () 1 k --- - 10.111mhz 34.6mhz ------------------------------ 63 () 1 1.257 -------------- - 14.647 == = bf f bw f xtal -------- br k ?? ?? 1 ? 34.6mhz 10.11mhz -------------------------- - 14 1.257 ?? ?? 1 ? 59.227 == =
ZL10038 data sheet 33 zarlink semiconductor inc. 5.0 application notes 5.1 thermal considerations figure 12 - copper dimensions for optimum heat transfer figure 13 - paste mask for reduced paste coverage the ZL10038 uses the 40-pin qfn package with a thermal ?paddle? in the base, which has a very high thermal conductivity to the die, as well as low electrical resistance to the vee connections. the ZL10038 has a fairly high power density, and if the excess heat is not efficiently removed, it will rapidly overheat beyond the 125c limit, and affect the performance or could even cause permanent damage to the device.
ZL10038 data sheet 34 zarlink semiconductor inc. the paddle is designed to be soldered to a size-matched pad on the pcb (see figure 10) which is thermally connected to an efficient heat sink. the heat sink can be as simple as an area of copper ground plane on the underside of the board, thereby reducing the system cost. to transfer the heat from the paddle to the underside of the board, an array of 25 x 03 mm? vias are used between the topside pad, which will be soldered to the paddle, and the ground plane on the underside of the board. it is also possible to use a smaller number of larger vias, e.g., 16 x 05 mm?, but this arrangement is marginally less efficient. the area of copper in the ground plane must be at least 2,000 mm2 for 1 oz copper. if 2 oz copper board is used or if multiple ground planes are available, as with a four-layer board, the area could be reduced somewhat, but in general it is better to have the maximum cooling possible, as reliability will always be enhanced if lower temperatures are maintained. while it is possible to use a paste mask that simply duplicates the aperture for the 4.15 mm sq. paddle, the quantity of solder paste under the device can cause problems and it is preferable to reduce the coverage to a level between 50% and 80% of the area. the pattern shown in figure 11 reduces the coverage to approximately 60%, which should reduce out-gassing from under the device and improve the stand-off height of the package from the board. a very useful publication giving further details is: ?application notes for surface mount assembly of amkorts microleadframe (mlf) packages? which can be found on: www.amkor.com 5.2 crystal oscillator notes figure 14 - typical oscillator arrangement with optional output figure 15 - typical arrangement for external oscillator component 4 mhz 10 mhz c10 47 pf 100 pf c11 47 pf 100 pf note: c12, a 10 pf (15 pf for 10 mhz) capacitor may be added between the crystal and gnd if an oscillator output is required. output is from the crystal/capacitor junction. table 19 - crystal capacitor values for 4 mhz and 10 mhz operation (component numbering refers to the example schematic, figure 2)
ZL10038 data sheet 35 zarlink semiconductor inc. 6.0 electrical characteristics 6.1 test conditions the following conditions apply to all figures in this chapter, except where notes indicate other settings. tamb = -10 to 85c, vee= 0 v, all vcc supplies = 5 v5% rf gain adjust = +0 db, prefilter = +4.2 db and postfilter = 4.2 db. rfg=0, ba1=0, ba0=1, bg1=0, bg0=1 these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. 6.2 absolute maximum ratings parameter symbol min. max. unit notes supply voltage vccbb, vccdig, vcclo, vccrf, vcctune -0.3 5.5 v w.r.t. vee storage temperature t stg -55 150 c junction temperature t j 125 c voltage on sda & scl -0.3 6 v vcc = vee to 5.25 v voltage on drive -0.3 vcctune+0.3 v voltage on rfin, rfbypass and inverted equivalents -0.3 vccrf+0.3 v voltage on rfagc voltage on vvar -0.3 vcclo+0.3 v voltage on lotest voltage on iout, qout, idc, qdc and inverted equivalents -0.3 vccbb+0.3 v voltage on p1 voltage at digdec -0.3 3.6 v voltage on pump -0.3 vccdig+0.3 v voltage on sleep and p0 voltage on add, xtal, xtalcap and lock -0.3 digdec+0.3 v sink current, p0 or p1 20 ma each output esd protection, pins 31 & 32 1 1. esd protection can be increased by adding a protection diode (d1) to the input circuit as shown in the application circuit ( figure 2). 0.5 kv to mil-std 883b method 3015 cat1 pins 1-30, 33-40 2.0 kv
ZL10038 data sheet 36 zarlink semiconductor inc. 6.3 recommended operating conditions 6.4 dc characteristics parameter symbol min. max. unit notes supply voltage vccbb, vccdig, vcclo, vccrf, vcctune 4.75 5.25 v w.r.t. vee operating temperature t op -10 85 c pins characteristic min. typ. max. units conditions normal operating conditions all vcc pins: 5, 6, 18, 19, 26, 29, 36, 37 supply current rf bypass filter b.w. 210 259 ma disabled minimum 228 281 ma maximum 243 300 ma enabled minimum 261 322 ma maximum 82 107 ma disabled sleep mode 115 ma enabled qout, qout , iout , iout: 3, 4, 7, 8 output impedance 25 ? single-ended output load 1 15 k ? pf maximum load, which can be applied to output, single-ended. if operated single ended unused output should be unloaded qdc, qdc , idc , idc: 1, 2, 9, 10 bias voltage 3.8 v output impedance 11 k ? scl, sda: 12, 13 input high voltage 2.3 5.5 v input low voltage 0 1 v input current -10 10 a input voltage =vee to vccdig leakage current 10 a input voltage = vee to 5.5 v, vccdig=vee hysteresis 0.4 v sda: 13 output voltage 0.4 v isink = 3 ma 0.6 v isink = 6 ma pump: 21 charge pump leakage +-3 +-20 na vpin = 1.8v charge pump current vpin = 1.8 v. see table 13 on page 26
ZL10038 data sheet 37 zarlink semiconductor inc. 6.5 ac characteristics drive: 20 max. voltage vcctune-0.2 v on-chip 3 kohm load resistor to vcctune min. voltage 0.3 v xtal, xtalcap: 14, 15 recommended crystal e.s.r. 10 200 ? parallel resonant crystal vvar: 23 input current -1 1 ma vee <= vvar <= 1.7 v (on-chip varactors forward biased) -25 25 a 1.7 v <= vvar <= vcc p0, p1: 24, 39 sink current 10 ma at vport = 0.7 v leakage current 10 a vport = vcc lock: 25 low output voltage 0.5 v out of lock at 1 ma high output voltage digdec-0.5 v in lock load current 1 ma add: 16 input high current 1 ma vin=digdec input low current -0.5 ma vin=vee sleep: 11 input high voltage 2 3.6 v sleep enabled input low voltage vee 0.5 v normal mode input dc current 10 a vin=vee to digdec rfagc: 34 leakage current -150 150 a vee <= vagc<= vcc lotest: 38 output impedance 100 ? bias voltage 3.3 v characteristic min. typ. max. units conditions system (see 1 ) noise figure, dsb 9 db at -70 dbm operating level 2 12 db at -60 dbm operating level 2 10 db at -70 dbm operating level 13 db at -60 dbm operating level variation in nf with rf gain adjust -1 db/db above ?60 dbm operating level 2 see figure 8 on page 15 conversion gain maximum minimum 72 78 610 db db vagc = 0.75 v vagc = 4.25 v agc control range 68 72 db agc monotonic, vagc from vee to vcc pins characteristic min. typ. max. units conditions
ZL10038 data sheet 38 zarlink semiconductor inc. system im2 -35 -40 dbc dbc see 3 see 4 system im3 -15 dbc see 5 variation in system second order intermodulation intercept -1 db/db see figure 6 on page 14 and 6 variation in system third order intermodulation intercept -1 db/db see figure 7 on page 14 and 7 input compression -10 -6 dbm see 8 lo second harmonic interference level -50 -35 dbc see 9 , all gain settings lna second harmonic interference level -35 -20 dbc see 10 quadrature gain match -0.6 0.6 db filter bandwidth settings 8-35 mhz, up to 0.8 x filter -3 db bandwidth quadrature phase match -3 3 deg i & q channel in band ripple 1 db i/q crosstalk 21 db synthesizer and other spurii on i & q outputs -30 dbc all gain settings below 68 db -25 dbc at maximum gain. linearly interpolated between max. and 68 db gain, see 11 lo reference sideband spur level on i & q outputs -40 dbc synthesizer phase detector comparison frequency 500-2000 khz in band lo leakage to rf input -65 dbm within rf band 950-2150 mhz -55 dbm within rf band 30-950 mhz rf bypass gain 1.5 5.5 db nf 10 13 db opip3 9 dbm see 12 opip2 26 dbm see 13 output return loss 9 db z 0 = 75 ? . see figure 9 on page 16, with output matching as in figure 2 on page 2. bypass enabled or disabled. forward isolation 25 db 950-2150 mhz single-ended to single-ended, bypass disabled reverse isolation 25 db in band lo leakage -65 dbm converter converter input return loss (pins rfin & rfin ) 810 dbz 0 = 75 ? . see figure 9 on page 16. with input matching as in figure 2 on page 2. bypass enabled or disabled characteristic min. typ. max. units conditions
ZL10038 data sheet 39 zarlink semiconductor inc. l.o. ssb phase noise -84 -84 -108 dbc/hz dbc/hz dbc/hz @ 1 khz offset @ 10 khz offset @ 100 khz offset measured either, at baseband output of 10 mhz, pll loop bandwidth circa 15 khz, or at lotest output 14 . -120 -110 -132 dbc/hz dbc/hz @ 1 mhz offset noise floor. measured at lotest output. l.o. integrated phase jitter 2 deg see 15 lotest output amplitude 200 mvp-p test output enabled into 50 ? baseband filters (specifications apply with both single-ended and differential load unless otherwise stated) bandwidth 4 40 mhz see 2.4, ?baseband filter? on page 16. maximum load as specified bandwidth absolute tolerance -5 +5 % filter bandwidth setting, fset, 8-35 mhz. slave oscillator enabled, see 16 channel bandwidth match -1 +1 % filter bandwidth settings 8-35 mhz characteristic response all bandwidth settings, see figure on page 17 channel gain match included in system gain match channel phase match output total harmonic distortion -26 dbc at 0.8 v p-p, single-ended. maximum load as specified output limiting 1.0 vp-p level at hard clipping, single-ended. maximum load as specified synthesizer crystal frequency 4 20 mhz see table 19 on page 34. external reference input frequency 420mhz sinewave coupled through 10 nf blocking capacitor to pin xtal. xtalcap is left open. external reference drive level 0.2 0.5 vp-p phase detector comparison frequency 31.25 2000 khz equivalent phase noise at phase detector -148 dbc/hz ssb, within loop bandwidth. phase detector comparison frequency = 1 mhz lo division ratio 240 32767 maximum scl clock rate 100 khz 1. all power levels are referred to 75 ? and assume an ideal impedance match: 0 dbm = 109 dbmv. system specifications refer to total cascaded system of converter/agc stage and baseband amplifier/filter stage with maximum terminating load as specified in ?recommended operating conditions? on page 36, with output amplitude of 0.5 vp-p differential. 2. see figure 8, rf gain adjust = +4 db, prefilter = +4.2 db and postfilter = 0 db, rfg = 1, ba1 = 0, ba0 = 1, bg1 = 0, bg0 = 0 3. ?baseband defined im2?. agc set to deliver an output of 0.5 vp-p with an input cw @ frequency fc of -25 dbm. two undesired tones at fc+146 and fc+155 mhz @ -11 dbm generating output intermodulation spur at 9 mhz. baseband filter at 22 mhz bandwidth setting. characteristic min. typ. max. units conditions
ZL10038 data sheet 40 zarlink semiconductor inc. 4. ?front end defined im2?. lo set to 2145 mhz and agc set to deliver a 5 mhz output of 0.5 vp-p with a desired input cw @ frequency 2150 mhz of -45 dbm. sum im2 product from two undesired tones at 1.05 and 1.1 ghz at -25 dbm converted to 5 mhz baseband with desired input removed. baseband filter at 22 mhz bandwidth setting. 5. ?im3?. agc set to deliver an output of 0.5 vp-p with an input cw @ frequency fc of -30 dbm. two undesired tones at fc+55 and fc+105 mhz at -11 dbm generating output intermodulation spur at 5 mhz. baseband filter at 22 mhz bandwidth setting. 6. ?front end defined? variation in ip2 from two undesired tones at 1.05 and 1.1 ghz at 20 dbc relative to desired at 2.15 ghz converted to 5 mhz baseband with lo tuned to 2.145 ghz with agc set to deliver 0.5 vp-p differential on desired, as desired amplitude is varied from -45 dbm to -75 dbm. 7. variation in ip3 product from two undesired tones at fc+55 and fc+105 mhz at 19 dbc relative to desired at fc converted to 5 mh z baseband with lo tuned to desired at fc ghz with agc set to deliver 0.5 vp-p differential on desired, as desired amplitude is varied from -30 dbm to -75 dbm. 8. agc set to deliver an output of 0.5 vp-p with an input cw @ frequency fc of -35 dbm. input compression defined as the level of interferer at 100 mhz offset, which leads to a 1 db compression in gain. 9. the level of 2.01 ghz downconverted to baseband relative to 1.01 ghz with the oscillator tuned to 1 ghz, measured with no input pre-filtering. 10. the level of second harmonic of 1.01 ghz input at -20 dbm downconverted to baseband relative to 2.01 ghz at -35 dbm with the oscillator tuned to 2 ghz, measured with no input pre-filtering gain set to deliver 0.5 vp-p on 2.01 ghz cw signal. rf gain adjust = +4 db, prefilter = +4.2 db and postfilter = 0 db rfg = 1, ba1 = 0, ba0 = 1, bg1 = 0, bg0 = 0 11. within 0-100 mhz band, rf input set to deliver 0.5 vp-p on output. rf gain adjust = +4 db, prefilter = +4.2 db and postfilter = 0 db rfg = 1, ba1 = 0, ba0 = 1, bg1 = 0, bg0 = 0 12. two input tones at fc+50 and fc+100 mhz at -9 dbm generating output intermodulation spur at fc. 13. sum im2 product from two input tones at 1.05 and 1.1 ghz at -9 dbm converted to 2150 mhz. 14. pll loop bandwidth ~15 khz, comparison frequency 1 - 2 mhz. 15. integrated rms lo jitter measured from 1 khz to 15 mhz, pll loop bandwidth 15 khz. varactor voltage = 3.5 volts. 16. rsd = 0 for 8 mhz <= fset <= 20 mhz, rsd = 1 for 20 mhz <= fset <= 35 mhz.
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